We develop a single AI chip solution for cost-effective edge devices that are not necessarily connected to the cloud for computation all the time.
Our non-volatile neural network solution is implemented in a standard CMOS process. Patent pending analog and Flash memory IPs are integrated in a single chip to provide energy efficient and cost effective AI solution.
A diverse group of talented hardware and software engineers, advisors, and consultants. Executives have a combined 50+ years of experience.
Anaflash is mentioned in the IEEE spectrum article: Searching for the perfect artificial synapse for AI. Check out more details from HERE.
Flash memory is in my opinion the NVM technology with the highest chance of enabling large scale computer-in-memory systems for ML and AI applications.
Prof. Chris H Kim at Univ. MinnesotaFounding Advisor of Anaflash
Anaflash's solution valued as "This approach is appealing because it depends on mature, well-understood component technologies." Check out more details from HERE.
Edge computing with some degree of AI capability is a massive trend. We seek to build a cost-effective non-volatile neural network accelerator IP for edge devices.
Dr. Sang-Soo LeeCEO of Anaflash
Anaflash Inc. (San Jose, CA) is a startup company that has developed a test chip to demonstrate analog neurocomputing taking place inside logic-compatible embedded flash memory. Check out more details from HERE.
We have received the SBIR Phase I contract award on our proposal titled “Reliable Logic Compatible Embedded Flash for Cost-Effective Secure SoC.”
AFRL (Air Force Research Lab) and AFWERX have partnered to streamline the Small Business Innovation Research process in an attempt to speed up the experience, broaden the pool of potential applicants and decrease bureaucratic overhead. Beginning in SBIR 18.2, and now in 19.1, the Air Force has begun offering 'Special' SBIR topics that are faster, leaner and open to a broader range of innovations.'
We have received the SBIR Phase I grant award on our proposal titled "Energy Efficient Neural Network Accelerator Featuring a Logic Compatible Non-Volatile Synapse Array." Check out more details from HERE.
Our paper in collaboration with University of Minnesota was presented on Dec 4 in 2018 IEEE International Electron Devices Meeting (IEDM), titled "A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic-Compatible Embedded Flash Memory Technology." Published paper is available from HERE.